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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TEMPERATURE RANGE
With the commercial (standard) temperature option the device operates over the temperature range 0 C to a 70 C The express temperature option provides b 40 C to a 85 C device operation
PROCESS INFORMATION
This device is manufactured on a complimentary high-performance metal-oxide semiconductor (CHMOS) process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook (order number 210997) All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation Values change depending on operating conditions and application requirements The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology Table 2 Thermal Characteristics Package Type 44-Lead PLCC 40-Pin PDIP iJA 46 C W 45 C W iJC 16 C W 16 C W
PROLIFERATION OPTIONS
Table 1 lists the proliferation options See Figure 2 for the 8XC151SA SB family nomenclature Table 1 Proliferation Options 8XC151SA SB (0 MHz-16 MHz 5V g10%) 80C151SB 83C151SA 83C151SB 87C151SA 87C151SB CPU-only 8K ROM 16K ROM 8K OTPROM 16K OTPROM
PACKAGE OPTIONS
Table 3 lists the 8XC151SA SB packages Table 3 Package Information Pkg N P TN TP Definition 44-Lead PLCC 40-Pin Plastic DIP 44-Lead PLCC 40-Pin Plastic DIP Temperature 0 C to a 70 C 0 C to a 70 C
b 40 C to a 85 C b 40 C to a 85 C
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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Figure 2 The 8XC151SA SB Family Nomenclature Table 4 Description of Product Nomenclature Parameter Temperature and Burn-in Options Options no mark T Packaging Options N P Program Memory Options 0 3 7 Process Information Product Family Device Memory Options Device Speed C 151 SA SB 16 Description Commercial operating temperature range (0 C to 70 C) with Intel standard burn-in Express operating temperature range ( b 40 C to 85 C) with Intel standard burn-in 44-lead Plastic Leaded Chip Carrier (PLCC) 40-pin Plastic Dual In-line Package (PDIP) Without ROM OTPROM ROM User programmable OTPROM CHMOS 8-bit controller architecture 256 bytes RAM 8 16 Kbyte ROM OTPROM or without ROM OTPROM External clock frequency
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Figure 3 8XC151SA SB 44-Lead PLCC Package
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Figure 4 8XC151SA SB 40-Pin PDIP and Ceramic DIP Packages
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5 PLCC DIP Signal Assignment Arranged by Functional Categories Address Name AD0 P0 0 AD1 P0 1 AD2 P0 2 AD3 P0 3 AD4 P0 4 AD5 P0 5 AD6 P0 6 AD7 P0 7 A8 P2 0 A9 P2 1 A10 P2 2 A11 P2 3 A12 P2 4 A13 P2 5 A14 P2 6 A15 P2 7 Data DIP 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 Name VCC VCC2 Processsor Control Name P3 2 INT0 P3 3 INT1 EA RST XTAL1 XTAL2 VPP PLCC 14 15 35 10 21 20 DIP 12 13 31 9 18 19 Name P3 6 WR P3 7 RD ALE PROG PSEN Bus Control Status PLCC 18 19 33 32 DIP 16 17 30 29 VSS VSS1 VSS2 EA VPP Power Ground PLCC 44 12 22 1 23 34 35 31 20 DIP 40 Name P1 0 T2 P1 1 T2EX P1 2 ECI P1 3 CEX0 P1 4 CEX1 P1 5 CEX2 P1 6 CEX3 P1 7 CEX4 P3 0 RXD P3 1 TXD P3 4 T0 P3 5 T1 Input Output PLCC 2 3 4 5 6 7 8 9 11 13 16 17 DIP 1 2 3 4 5 6 7 8 10 11 14 15
PLCC 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6 Signal Assignments Arranged by Package Number PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 DIP Name VSS1 P1 0 T2 P1 1 T2EX P1 2 ECI P1 3 CEX0 P1 4 CEX1 P1 5 CEX2 P1 6 CEX3 P1 7 CEX4 RST P3 0 RXD VCC2 P3 1 TXD P3 2 INT0 P3 3 INT1 P3 4 T0 P3 5 T1 P3 6 WR P3 7 RD XTAL2 XTAL1 VSS PLCC 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 DIP Name VSS2 A8 P2 0 A9 P2 1 A10 P2 2 A11 P2 3 A12 P2 4 A13 P2 5 A14 P2 6 A15 P2 7 PSEN ALE PROG VSS2 EA Vpp AD7 P0 7 AD6 P0 6 AD5 P0 5 AD4 P0 4 AD3 P0 3 AD2 P0 2 AD1 P0 1 AD0 P0 0 VCC
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SIGNAL DESCRIPTIONS
Table 7 Signal Descriptions Signal Name A15 8 AD7 0 ALE Type O IO O Description Address Lines Upper address lines for the external bus Address Data Lines Multiplexed lower address lines and data lines for external memory Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus Programmable Counter Array (PCA) Input Output Pins These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode External Access Directs program memory accesses to on-chip or off-chip code memory For EA e 0 all program memory accesses are off-chip For EA e 1 an access is to on-chip ROM OTPROM if the address is within the range of the on-chip ROM OTPROM otherwise the access is off-chip The value of EA is latched at reset For devices without on-chip ROM OTPROM EA must be strapped to ground PCA External Clock Input External clock input to the 16-bit PCA timer External Interrupts 0 and 1 These inputs set bits IE1 0 in the TCON register If bits IT1 0 in the TCON register are set bits IE1 0 are set by a falling edge on INT1 INT0 If bits INT1 0 are clear bits IE1 0 are set by a low level on INT1 0 Programming Pulse The programming pulse is applied to this pin for programming the on-chip OTPROM Port 0 This is an 8-bit open-drain bidirectional I O port Port 1 This is an 8-bit bidirectional I O port with internal pullups Multiplexed With P2 7 0 P0 7 0 PROG
CEX4 0
IO
P1 6 3 P1 7 VPP
EA
I
ECI INT1 0
I I
P1 2 P3 3 2
PROG P0 7 0 P1 0 P1 1 P1 2 P1 7 3 P2 7 0
I IO IO
ALE AD7 0 T2 T2EX ECI CEX3 0 CEX4 A15 8
IO
Port 2 This is an 8-bit bidirectional I O port with internal pullups
The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers) If the chip is configured for page-mode operation port 0 carries the lower address bits (A7 0) and port 2 carries the upper address bits (A15 8) and the data (D7 0)
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 7 Signal Descriptions (Continued) Signal Name P3 0 P3 1 P3 3 2 P3 5 4 P3 6 P3 7 PSEN Type IO Description Port 3 This is an 8-bit bidirectional I O port with internal pullups Multiplexed With RXD TXD INT1 0 T1 0 WR RD
O
Program Store Enable Read signal output This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 Read Read signal output to external data memory Reset Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied whether or not the oscillator is running This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and VCC Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation P3 7
RD RST
O I
RXD T1 0 T2
IO I IO
Receive Serial Data RXD sends and receives data in serial I O mode 0 and receives data in serial I O modes 1 2 and 3 Timer 1 0 External Clock Inputs When timer 1 0 operates as a counter a falling edge on the T1 0 pin increments the count Timer 2 Clock Input Output For the timer 2 capture mode this signal is the external clock input For the clock-out mode it is the timer 2 clock output Timer 2 External Input In timer 2 capture mode a falling edge initiates a capture of the timer 2 registers In auto-reload mode a falling edge causes the timer 2 registers to be reloaded In the updown counter mode this signal determines the count direction 1 e up 0 e down Transmit Serial Data TXD outputs the shift clock in serial I O mode 0 and transmits serial data in serial I O modes 1 2 and 3 Supply Voltage Connect this pin to the a 5V supply voltage Secondary Supply Voltage 2 This supply voltage connection is provided to reduce power supply noise Connection of this pin to the a 5V supply voltage is recommended However when using the 8XC151SA SB as a pin-for-pin replacement for the 8XC51FX VSS2 can be unconnected without loss of compatibility (Not available on DIP) Programming Supply Voltage The programming supply voltage is applied to this pin for programming the on-chip OTPROM
P3 0 P3 5 4 P1 0
T2EX
I
P1 1
TXD VCC VCC2
O PWR PWR
P3 1
VPP
I
EA
The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers) If the chip is configured for page-mode operation port 0 carries the lower address bits (A7 0) and port 2 carries the upper address bits (A15 8) and the data (D7 0)
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 7 Signal Descriptions (Continued) Signal Name VSS VSS1 Type GND GND Description Circuit Ground Connect this pin to ground Secondary Ground This ground is provided to reduce ground bounce and improve power supply bypassing Connection of this pin to ground is recommended However when using the 8XC151SA SB as a pinfor-pin replacement for the 8XC51BH VSS1 can be unconnected without loss of compatibility (Not available on DIP) Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing Connection of this pin to ground is recommended However when using the 8XC151SA SB as a pin-for-pin replacement for the 8XC51FX VSS2 can be unconnected without loss of compatibility (Not available on DIP) Write Write signal output to external memory Input to the On-chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used its output is connected to this pin XTAL1 is the clock source for internal timing Output of the On-chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used leave XTAL2 unconnected P3 6 Multiplexed With
VSS2
GND
WR XTAL1
O I
XTAL2
O
The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers) If the chip is configured for page-mode operation port 0 carries the lower address bits (A7 0) and port 2 carries the upper address bits (A15 8) and the data (D7 0)
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias Commercial 0 C to a 70 C b 40 C to a 85 C Express b 65 C to a 150 C Storage Temperature Voltage on EA VPP Pin to VSS 0V to a 13 0V b 0 5V to a 6 5V Voltage on Any other Pin to VSS IOL per I O Pin Power Dissipation NOTE Maximum power dissipation is based on package heat-transfer limitations not device power consumption 15 mA 1 5W
NOTICE This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias) Commercial 0 C to a 70 C b 40 C to a 85 C Express VCC (Digital Supply Voltage) 4 5V to 5 5V VSS 0V
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
DC CHARACTERISTICS
Parameter values apply to all devices unless otherwise indicated Table 8 DC Characteristics at VCC e 4 5V b 5 5V Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage (except EA ) Input Low Voltage (EA ) Input High Voltage (except XTAL1 RST) Input High Voltage (XTAL1 RST) Output Low Voltage (Port 1 2 3) Min
b0 5
Typical
Max 0 2VCC b 0 1 0 2VCC b 0 3 VCC a 0 5 VCC a 0 5 03 0 45 10 03 0 45 10
Units V V V V V
Test Conditions
0 0 2VCC a 0 9 0 7VCC
IOL e 100 mA IOL e 1 6 mA IOL e 3 5 mA (Note 1 Note 2) IOL e 200 mA IOL e 3 2 mA IOL e 7 0 mA (Note 1 Note 2) IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA (Note 3)
VOL1
Output Low Voltage (Port 0 ALE PSEN )
V
VOH
Output High Voltage (Port 1 2 3 ALE PSEN )
VCC b 0 3 VCC b 0 7 VCC b 1 5
V
NOTES 1 Under steady-state (non-transient) conditions IOL must be externally limited as follows Maximum IOL per port pin 10 mA Maximum IOL per 8-bit port port 0 26 mA ports 1-3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0 4V on the low-level outputs of ALE and ports 1 2 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic 3 Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the specification when the address lines are stabilizing 4 Typical values are obtained using VCC e 5 0 TA e 25 C and are not guaranteed
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8 DC Characteristics at VCC e 4 5V b 5 5V (Continued) Symbol VOH1 Parameter Output High Voltage (Port 0 in External Address) Output High Voltage (Port 2 in External Address during Page Mode) Logical 0 Input Current (Port 1 2 3) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Port 1 2 3) RST Pulldown Resistor Pin Capacitance Powerdown Current Idle Mode Current Operating Current 40 10 (Note 4) 10 (Note 4) 13 (Note 4) 71 (Note 4)
k 20
Min VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5
Typical
Max
Units V
Test Conditions IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 0 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 0 mA VIN e 0 45V 0 45 k VIN k VCC VIN e 2 0V
VOH2
V
IIL ILI ITL
b 50
mA mA mA
g10
b 650
RRST CIO IPD IDL ICC
225
kX pF mA mA mA FOSC e 16 MHz FOSC e 16 MHz FOSC e 16 MHz TA e 25 C
20 85
NOTES 1 Under steady-state (non-transient) conditions IOL must be externally limited as follows Maximum IOL per port pin 10 mA Maximum IOL per 8-bit port port 0 26 mA ports 1-3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0 4V on the low-level outputs of ALE and ports 1 2 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic 3 Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the specification when the address lines are stabilizing 4 Typical values are obtained using VCC e 5 0 TA e 25 C and are not guaranteed
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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All other 8XC151SA SB pins are unconnected
Figure 5 IPD Test Condition Powerdown Mode VCC e 2 0V b 5 5V
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
state and Notes 4 and 5 mark parameters affected by a PSEN RD WR wait state Figures 5 - 11 show the bus cycles with the timing parameters
AC Characteristics
Table 8 lists AC timing parameters for the 8XC151SA SB with no wait states External wait states can be added by extending PSEN RD WR and or by extending ALE In the table Notes 3 and 5 mark parameters affected by an ALE wait
Table 9 AC Characteristics (Capacitive Loading e 50 pF) Symbol FOSC TOSC Parameter XTAL1 Frequency 1 FOSC 12 MHz 16 MHz TLHLL ALE Pulse Width 12 MHz 16 MHz Address Valid to ALE Low 12 MHz 16 MHz Address Hold after ALE Low 12 MHz 16 MHz RD or PSEN Pulse Width 12 MHz 16 MHz Pulse Width 12 MHz 16 MHz Low 58 3 37 5 83 3 62 5 Tosc b 25 ns (3) (1 a 2M) TOSC 68 3 47 5 Max FOSC (1) Min NA NA Max NA NA 83 3 62 5 ns (3) (1 a 2M) TOSC b 15 ns (3) (1 a 2M) TOSC b 25 ns 10 10 151 6 110 10 ns (4) 2(1 a N) TOSC b 15 ns (4) 2(1 a N) TOSC b 15 ns FOSC Variable Min 0 Max 16 MHz ns Units
TAVLL
58 3 37 5
TLLAX
TRLRH (2)
TWLWH
WR
151 6 110
TLLRL (2)
ALE Low to RD or PSEN 12 MHz 16 MHz ALE High to Address Hold 12 MHz 16 MHz
TLHAX
NOTES 1 16 MHz 2 Specifications for PSEN are identical to those for RD 3 In the formula M e Number of wait states (0 or 1) for ALE 4 In the formula N e Number of wait states (0 1 2 or 3) for RD 5 ``Typical'' specifications are untested and not guaranteed
PSEN
WR
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 9 AC Characteristics (Capacitive Loading e 50 pF) (Continued) Symbol TRLDV (2) RD Parameter PSEN Low to valid Data Instruction In 12 MHz 16 MHz Max FOSC (1) Min Max 111 6 70 FOSC Variable Min Max ns (4) 2(1 a N) TOSC b 55 0 2 Typ e 0 (5) 2 ns ns ns 0 0 High 151 6 110 2TOSC b 15 ns 0 0 156 6 115 166 6 125 253 2 170 0 ns 2TOSC b 10 ns 2TOSC ns (3) 4(1 a M 2) TOSC b 80 ns (3) 4(1 a M 2) TOSC b 65 ns 116 6 75 2TOSC b 50 0 ns Units
TRHDX (2) RD PSEN Data Instruction Hold after RD and PSEN High TRLAZ (2) RD TRHDZ1 PSEN Low to Address Float PSEN High
0 Typ e 0 (5)
Instruction Float after RD 12 MHz 16 MHz Data Float after RD 12 MHz 16 MHz RD
TRHDZ2
PSEN
TRHLH1
PSEN High to ALE High (Instruction) 12 MHz 16 MHz PSEN High to ALE High (Data) 12 MHz 16 MHz High to ALE High 12 MHz 16 MHz
TRHLH2
RD
TWHLH
WR
TAVDV1
Address (P0) Valid to Valid Data Instruction In 12 MHz 16 MHz Address (P2) Valid to Valid Data Instruction In 12 MHz 16 MHz Address (P0) Valid to Valid Instruction In 12 MHz 16 MHz
TAVDV2
268 2 185
TAVDV3
NOTES 1 16 MHz 2 Specifications for PSEN are identical to those for RD 3 In the formula M e Number of wait states (0 or 1) for ALE 4 In the formula N e Number of wait states (0 1 2 or 3) for RD 5 ``Typical'' specifications are untested and not guaranteed
PSEN
WR
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 9 AC Characteristics (Capacitive Loading e 50 pF) (Continued) Symbol TAVRL (2) Parameter Address Valid to RD 12 MHz 16 MHz PSEN Low 126 6 85 Low 126 6 85 Low 141 6 100 2(1 a M) TOSC b 25 ns 58 3 37 5 146 6 105 TOSC b 25 ns (4) 2(1 a N) TOSC b 20 ns 146 6 105 2TOSC b 20 2(1 a M) TOSC b 40 ns (3) 2(1 a M) TOSC b 40 ns (3) Max FOSC (1) Min Max FOSC Variable Min Max ns (3) Units
TAVWL1
Address (P0) Valid to WR 12 MHz 16 MHz Address (P2) Valid to WR 12 MHz 16 MHz Data Hold after WR 12 MHz 16 MHz High
TAVWL2
TWHQX
TQVWH
Data Valid to WR High 12 MHz 16 MHz WR High to Address Hold 12 MHz 16 MHz
TWHAX
NOTES 1 16 MHz 2 Specifications for PSEN are identical to those for RD 3 In the formula M e Number of wait states (0 or 1) for ALE 4 In the formula N e Number of wait states (0 1 2 or 3) for RD 5 ``Typical'' specifications are untested and not guaranteed
PSEN
WR
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SYSTEM BUS TIMINGS
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The value of this parameter depends on wait states See the table of AC characteristics
Figure 6 External Read Data Bus Cycle in Nonpage Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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The value of this parameter depends on wait states See the table of AC characteristics
Figure 7 External Instruction Bus Cycle in Nonpage Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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The value of this parameter depends on wait states See the table of AC characteristics
Figure 8 External Write Data Bus Cycle in Nonpage Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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The value of this parameter depends on wait states See the table of AC characteristics
Figure 9 External Read Data Bus Cycle in Page Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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The value of this parameter depends on wait states See the table of AC characteristics
Figure 10 External Write Data Bus Cycle in Page Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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The value of this parameter depends on wait states See the table of AC characteristics A page hit (i e a code fetch to the same 256-byte ``page'' as the previous code fetch) requires one state (2TOSC) a page miss requires two states (4TOSC) During a sequence of page hits PSEN remains low until the end of the last page-hit cycle
Figure 11 External Instruction Bus Cycle in Page Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
AC Characteristics
Symbol TXLXL TQVSH TXHQX TXHDX TXHDV
Serial Port Shift Register Mode
Table 10 Serial Port Timing Shift Register Mode Parameter Min 12TOSC 10TOSC b 133 2TOSC b 117 0 10TOSC b 133 Max Units ns ns ns ns ns
Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid
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TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit
Figure 12 Serial Port Waveform
Shift Register Mode
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
External Clock Drive
Table 11 External Clock Drive Symbol 1 TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency (FOSC) High Time Low Time Rise Time Fall Time 20 20 10 10 Min Max 16 Units MHz ns ns ns ns
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Figure 13 External Clock Drive Waveforms
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AC inputs during testing are driven at VCC b 0 5V for a logic 1 and 0 45V for a logic 0 Timing measurements are made at a min of VIH for logic 1 and VOL for a logic 0
Figure 14 AC Testing Input Output Waveforms
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH VOL level occurs with IOL IOH e g20 mA
Figure 15 Float Waveforms
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Figure 16 Setup for Programming and Verifying Nonvolatile Memory
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Information in Figures 17 and 18 define the configuration bits Figure 19 shows the waveforms for the programming and verification cycles and Table 12 lists the timing specifications The signature bytes of the 83C151SA SB ROM versions and the 87C151SA SB OTPROM versions are factory programmed Table 13 lists the addresses and the contents of the signature bytes Factory-programmed ROM and OTPROM versions of 8XC151SA SB use configuration byte information supplied in a separate hexadecimal disk file 8XC151SA SB devices without internal ROM OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9 8H NOTE The VPP source in Figure 16 must be well regulated and free of glitches The voltage on the VPP pin must not exceed the specified maximum even under transient conditions
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
The 87C151SA SB has several areas of nonvolatile memory that can be programmed and or verified on-chip code memory (8 16 Kbytes) lock bits (3 bits) encryption array (128 bytes) and signature bytes (3 bytes) Figure 16 shows the setup for programming and or verifying the nonvolatile memory Table 11 lists the programming and verification operations and indicates which operations apply to the different versions of the 87C151SA SB It also specifies the signals on the programming input (PROG ) and the ports The ROM OTPROM mode (port 0) specifies the operation (program or verify) and the base address of the memory area The addresses (ports 1 and 3) are relative to the base address (On-chip memory for a 16-Kbyte ROM OTPROM device is located at address range 0000H-3FFFH The other areas of the ROM OTPROM are outside the memory address space and are accessible only during programming and verification )
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 12 Programming and Verification Modes Mode Mode 8XC151SA SB Xe7 Program On-Chip Code Memory Verify On-Chip Code Memory Program Configuration Bytes Verify Configuration Bytes Program Lock Bits Verify Lock Bits Program Encryption Array Verify Signature Bytes Y Y Y Y Y Y 25 Pulses High 25 Pulses High 6BH 2BH 6CH 29H XX Data Data Data 0001H - 0003H 0000H 0000H - 007FH 0030H 0031H 0060H Y Y Y Xe3 5 Pulses High 68H 28H Data Data 0000H - 3FFFH (16K) 0000H - 1FFFH (8K) 0000H - 3FFFH (16K) 0000H - 1FFFH (8K) 2 2 13 4 1 1 PROG P0 P2 Addresses P1 (high) P3 (low) Notes
NOTES 1 The PROG pulse waveform is shown in Figure 19 2 Factory-programmed ROM and OTPROM versions of 8XC151SA SB use configuration byte information supplied in a separate hexadecimal disk file 8XC151SA SB devices without internal ROM OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9 8H 3 When programming the lock bits the data bits on port 2 are don't care Identify the lock bits with the address as follows LB3 - 0003H LB2 - 0002H LB1 - 0001H 4 The three lock bits are verified in a single operation The states of the lock bits appear simultaneously at port 2 as follows LB3 - P2 3 LB2 - P2 2 LB1 - P2 1 High e programmed
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Address FFF8H 0 WSA1 WSA0 XALE PAGE
UCONFIG0 7
Bit Number 7 65
Bit Mnemonic Reserved WSA1 WSA0 (see Note)
Function
Wait State Select for external code WSA1 WSA0 Description 1 1 No wait states 1 0 Insert 1 wait state 0 1 Insert 2 wait states 0 0 Insert 3 wait states Extend Ale If this bit is set the time of the ALE pulse is TOSC Clearing this bit extends the time of the ALE pulse from TOSC to 3TOSC which adds one external wait state Page Mode Select Clear this bit for page-mode (A15 8 D7 0 on P2 and A7 0 on P0) Set this bit for nonpage-mode (A15 8 on P2 and A7 0 D7 0 on P0 (compatible with MCS 51 microcontrollers))
4
XALE
1
PAGE
NOTE Factory-programmed ROM and OTPROM versions of 8XC151SA SB use configuration byte information supplied in a separate hexadecimal disk file 8XC151SA SB devices without internal ROM OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9 8H
Figure 17 Configuration Byte 0
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Address FFF9H 0 WSB1 WSB0
UCONFIG1 7
Bit Number 75 21
Bit Mnemonic
Function Reserved set these bits when writing to UCONFIG1
WSB1 WSB0
Wait States for external data WSB1 WSB0 Description 1 1 0 0 1 0 1 0 No wait states Insert 1 wait state Insert 2 wait states Insert 3 wait states
NOTE Factory-programmed ROM and OTPROM versions of 8XC151SA SB use configuration byte information supplied in a separate hexadecimal disk file 8XC151SA SB devices without internal ROM OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9 8H
Figure 18 Configuration Byte 1
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
272814 - 17
Figure 19 Timing for Programming and Verification of Nonvolatile Memory
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 13 Nonvolatile Memory Programming and Verification Characteristics at TA e 21 b 27 C VCC e 5V and VSS e 0V Symbol VPP IPP FOSC TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Definition Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Address Hold after PROG Data Setup to PROG Data Hold after PROG ENABLE High to VPP VPP Setup to PROG VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low 0 10 Low Low Low 40 48TOSC 48TOSC 48TOSC 48TOSC 48TOSC 10 10 90 110 48TOSC 48ToSC 48TOSC ms ms ms ms Min 12 5 Max 13 5 75 60 Units D C Volts mA MHz
NOTE Notation for timing parameters A e Address Q e Data out D e Data S e Supply (VPP) E e Enable V e Valid G e PROG X e No Longer Valid H e High Z e Floating L e Low
Table 14 Contents of the Signature Bytes ADDRESS 30H 31H 60H 60H 60H 60H CONTENTS 89H 48H 7BH FBH 7AH FAH DEVICE TYPE Indicates Intel Devices Indicates MCS 151 core product Indicates 83C151SB device Indicates 87C151SB device Indicates 83C151SA device Indicates 87C151SA device
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